1. Field of the Invention
The present invention relates to digital logic circuits, and more specifically to bit mapping within a digital logic circuit.
2. Description of the Related Art
In a low-level computer architecture's bitwise manipulation of data, some means of translating binary data left or right by a variable number of positions has often proved useful. For example, such translation, or shifting, of a binary value having a single 1 has been used to examine each bit in a data word. The value is shifted one bit position each clock cycle and then AND-ed with a test value, and used to examine each bit in the test value, one bit at a time. Shifting can also be used to perform simple multiplication (shift left) and division (shift right) by powers of two, albeit with a loss of precision if any 1s are shifted out of the data.
Shifters have traditionally been constructed as standalone functional units. Some trivial shifters provide for shifting left and right by only one position, relying on the programmer to synthesize shifts through repeated application of the shift primitives. A more general shifter increases performance through being able to shift an arbitrary number of places in a fixed amount of time.
To accomplish the more general shifting by an arbitrary number of places, shifters have typically been constructed from an array of multiplexers. The number of multiplexers has generally been equal to the length of the received data value, while the number of bits of the received data value has been equal to the maximum shift amount. The multiplexers have been fabricated of an array of CMOS logic gates provided with the select values. The select value has generally been a binary number between zero and the length of the string of consecutive bits, and therefore can be used to select one of the bits from the string. The received data value has been partitioned into substrings, each beginning with a different bit of the received data value, yet each having a number of bits equal to one more than the maximum shift amount. The substrings have contained a portion of the received data value. Substrings beginning near the end of received data value have been completed by using bits near the beginning of the received data value.
Each of the multiplexers has been provided with the same shift amount value, which has been used to select one bit to each multiplexer. Consequently each multiplexer has provided a distinct bit of an output data value.
While the shifter of the prior art has proven useful in simple static binary CMOS shifting, several assumptions have been "built in" to the prior art shifter that inhibit its usefulness to other logic styles. Specifically, the received data value has been implemented in wires each representing a bit, and the shift amount has represented a number of bits. In other words, both the received data value and the shift amount have a "granularity" measured in bits. Shifters have generally been designed with such an assumption, that the "granularity" of the shift amount and the "granularity" of the received data value have been presumed to be equal.
Moreover, the granularity of all data values has been presumed to be one bit. Each physical wire implementing any data value has corresponded to one bit of the value. Implementing data values as binary strings of bits, and assigning one physical wire to each bit, has imposed a doctrinaire logic style of one-bit granularity.
One notable exception to the above is dual-rail logic. Dual-rail logic has implemented each bit of a data value on a pair of physical wires, one wire is for the "True" of the signal and the other wire is for the "False" of the signal. However, the granularity of data values remains one-bit, even in dual-rail logic.